LaRosa Engineering

ENGINEERING

Free/Open hardware design.

LaRosa Engineering, under Noqsi Aerospace, ltd, has contributed FPGA designs for CCD Clock Sequencers developed at MIT. We are publishing the designs and documentation under a Creative Commons license.

Noqsi's Engineering page details ongoing engineering research at Noqsi. For a history/evolution of MIT CCD Clock Sequencers, click here.

This page details the logic design for an FPGA-based Sequencer, referred to on the last two pages of the above history/evolution document. The FPGA discussed here was designed from John Doty's CCD Clock Sequencer spec.

FPGA_Seq_2003.pdf provides a walk-through of the Sequencer VHDL design

Here are links to support documents:

EDCCD Xilinx Project
Sequencer Specification
Cypress CY7C1329 RAM Data Sheet

And some simulation outputs:
edccd_init_timing (INIT sequence and the start of the RAM loading)

edccd_cmd_timing
showing the first two Command FIFO loads, and the Sequencer logic starting up as soon as the first Command has been loaded.

edccd_output_timing
showing the walking one’s pattern in the 8 least significant bits, along with the output CLK and STRB signals.


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Home Services Projects Eng ineering Contact			ENGINEERING Free/Open hardware design. LaRosa Engineering, under Noqsi Aerospace, ltd, has contributed FPGA designs for CCD Clock Sequencers developed at MIT. We are publishing the designs and documentation under a Creative Commons license. Noqsi's Engineering page details ongoing engineering research at Noqsi. For a history/evolution of MIT CCD Clock Sequencers, click here. This page details the logic design for an FPGA-based Sequencer, referred to on the last two pages of the above history/evolution document. The FPGA discussed here was designed from John Doty's CCD Clock Sequencer spec. FPGA_Seq_2003.pdf provides a walk-through of the Sequencer VHDL design Here are links to support documents: EDCCD Xilinx Project Sequencer Specification Cypress CY7C1329 RAM Data Sheet And some simulation outputs: edccd_init_timing (INIT sequence and the start of the RAM loading) edccd_cmd_timing showing the first two Command FIFO loads, and the Sequencer logic starting up as soon as the first Command has been loaded. edccd_output_timing showing the walking one’s pattern in the 8 least significant bits, along with the output CLK and STRB signals.